Please use this identifier to cite or link to this item:
http://acervodigital.unesp.br/handle/11449/42030
- Title:
- A transactional runtime system for the Cell/BE architecture
- Universidade Estadual Paulista (UNESP)
- Universidade Estadual de Campinas (UNICAMP)
- 0743-7315
- IBM
- Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
- Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
- FAPESP: 11/19373-6
- Single-core architectures have hit the end of the road and industry and academia are currently exploiting new multicore design alternatives. In special, heterogeneous multicore architectures have attracted a lot of attention but developing applications for such architectures is not an easy task due to the lack of appropriate tools and programming models. We present the design of a runtime system for the Cell/BE architecture that works with memory transactions. Transactional programs are automatically instrumented by the compiler, shortening development time and avoiding synchronization mistakes usually present in lock-based approaches (such as deadlock). Experimental results conducted with a prototype implementation and the STAMP benchmark show good scalability for applications with moderate to low contention levels, and whose transactions are not too small. For those cases in which a small performance loss is admissible, we believe that the ease of programming provided by transactions greatly pays off. (C) 2012 Elsevier B.V. All rights reserved.
- 1-Dec-2012
- Journal of Parallel and Distributed Computing. San Diego: Academic Press Inc. Elsevier B.V., v. 72, n. 12, p. 1535-1546, 2012.
- 1535-1546
- Academic Press Inc. Elsevier B.V.
- Multiprocessors
- Parallel programming
- Transactional memory
- http://dx.doi.org/10.1016/j.jpdc.2012.08.001
- Acesso restrito
- outro
- http://repositorio.unesp.br/handle/11449/42030
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