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Please use this identifier to cite or link to this item: http://acervodigital.unesp.br/handle/11449/67969
Title: 
A petri net based timing model for hardware/software co-design of digital systems
Author(s): 
Institution: 
  • Universidade Estadual Paulista (UNESP)
  • Universidade Estadual de Campinas (UNICAMP)
Abstract: 
We have recently proposed an extension to Petri nets in order to be able to directly deal with all aspects of embedded digital systems. This extension is meant to be used as an internal model of our co-design environment. After analyzing relevant related work, and presenting a short introduction to our extension as a background material, we describe the details of the timing model we use in our approach, which is mainly based in Merlin's time model. We conclude the paper by discussing an example of its usage. © 2004 IEEE.
Issue Date: 
1-Dec-2004
Citation: 
IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, v. 1, p. 65-68.
Time Duration: 
65-68
Keywords: 
  • Computational complexity
  • Computer hardware
  • Computer science
  • Computer software
  • Embedded systems
  • Field programmable gate arrays
  • Mathematical models
  • Timing devices
  • Cooperative design (co-design)
  • Digital systems
  • Merlin's time model
  • Networks on chip (NoC)
  • Petri nets
Source: 
http://dx.doi.org/10.1109/APCCAS.2004.1412692
URI: 
Access Rights: 
Acesso restrito
Type: 
outro
Source:
http://repositorio.unesp.br/handle/11449/67969
Appears in Collections:Artigos, TCCs, Teses e Dissertações da Unesp

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