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Please use this identifier to cite or link to this item: http://acervodigital.unesp.br/handle/11449/73829
Title: 
Energy-performance tradeoffs in software transactional memory
Author(s): 
Institution: 
  • Universidade Estadual Paulista (UNESP)
  • Linux Technology Center - IBM
  • Universidade Estadual de Campinas (UNICAMP)
ISSN: 
1550-6533
Abstract: 
Transactional memory (TM) is a new synchronization mechanism devised to simplify parallel programming, thereby helping programmers to unleash the power of current multicore processors. Although software implementations of TM (STM) have been extensively analyzed in terms of runtime performance, little attention has been paid to an equally important constraint faced by nearly all computer systems: energy consumption. In this work we conduct a comprehensive study of energy and runtime tradeoff sin software transactional memory systems. We characterize the behavior of three state-of-the-art lock-based STM algorithms, along with three different conflict resolution schemes. As a result of this characterization, we propose a DVFS-based technique that can be integrated into the resolution policies so as to improve the energy-delay product (EDP). Experimental results show that our DVFS-enhanced policies are indeed beneficial for applications with high contention levels. Improvements of up to 59% in EDP can be observed in this scenario, with an average EDP reduction of 16% across the STAMP workloads. © 2012 IEEE.
Issue Date: 
1-Dec-2012
Citation: 
Proceedings - Symposium on Computer Architecture and High Performance Computing, p. 147-154.
Time Duration: 
147-154
Keywords: 
  • Energy Consumption
  • Parallel Computing
  • Transactional Memory
  • Comprehensive studies
  • Conflict Resolution
  • Energy delay product
  • Multi-core processor
  • Runtime performance
  • Runtimes
  • Software implementation
  • Software transactional memory
  • Synchronization mechanisms
  • Transactional memory
  • Computer architecture
  • Computer systems
  • Energy utilization
  • Parallel architectures
  • Parallel processing systems
  • Parallel programming
  • Storage allocation (computer)
  • Commerce
Source: 
http://dx.doi.org/10.1109/SBAC-PAD.2012.19
URI: 
Access Rights: 
Acesso restrito
Type: 
outro
Source:
http://repositorio.unesp.br/handle/11449/73829
Appears in Collections:Artigos, TCCs, Teses e Dissertações da Unesp

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