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http://acervodigital.unesp.br/handle/11449/122754
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DC Field | Value | Language |
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dc.contributor.author | Dias, Maurício Araújo | - |
dc.contributor.author | Gouveia, Márcio Ricardo Alves | - |
dc.contributor.author | Oliveira, José Raimundo de | - |
dc.contributor.author | Muñoz, Ignacio Bravo | - |
dc.date.accessioned | 2015-04-27T11:56:00Z | - |
dc.date.accessioned | 2016-10-25T20:46:59Z | - |
dc.date.available | 2015-04-27T11:56:00Z | - |
dc.date.available | 2016-10-25T20:46:59Z | - |
dc.date.issued | 2013 | - |
dc.identifier | http://www.diogenes.bg/ijam/contents/2013-26-2/10/ | - |
dc.identifier.citation | International Journal of Applied Mathematics, v. 26, n. 1, p. 241-262, 2013. | - |
dc.identifier.issn | 1311-1728 | - |
dc.identifier.uri | http://hdl.handle.net/11449/122754 | - |
dc.identifier.uri | http://acervodigital.unesp.br/handle/11449/122754 | - |
dc.description.abstract | This paper presents the design of a high-speed coprocessor for Elliptic Curve Cryptography over binary Galois Field (ECC- GF(2m)). The purpose of our coprocessor is to accelerate the scalar multiplication performed over elliptic curve points represented by affine coordinates in polynomial basis. Our method consists of using elliptic curve parameters over GF(2163) in accordance with international security requirements to implement a bit-parallel coprocessor on field-programmable gate-array (FPGA). Our coprocessor performs modular inversion by using a process based on the Stein's algorithm. Results are presented and compared to results of other related works. We conclude that our coprocessor is suitable for comparing with any other ECC-hardware proposal, since its speed is comparable to projective coordinate designs. | en |
dc.format.extent | 241-262 | - |
dc.language.iso | eng | - |
dc.source | Currículo Lattes | - |
dc.subject | elliptic curves | en |
dc.subject | GF(2m) | en |
dc.subject | cryptography | en |
dc.subject | bit-parallel | en |
dc.subject | coprocessor | en |
dc.subject | FPGA | en |
dc.title | Bit-parallel coprocessor for standard ECC-GF(2m) on FPGA | en |
dc.type | outro | - |
dc.contributor.institution | Universidade Estadual Paulista (UNESP) | - |
dc.description.affiliation | Universidade Estadual Paulista Júlio de Mesquita Filho, Instituto de Biociências Letras e Ciências Exatas de São José do Rio Preto, Sao Jose do Rio Preto, Rua Cristóvão Colombo, 2265, Jardim Nazareth, CEP 15054-000, SP, Brasil | - |
dc.description.affiliationUnesp | Universidade Estadual Paulista Júlio de Mesquita Filho, Instituto de Biociências Letras e Ciências Exatas de São José do Rio Preto, Sao Jose do Rio Preto, Rua Cristóvão Colombo, 2265, Jardim Nazareth, CEP 15054-000, SP, Brasil | - |
dc.description.affiliationUnesp | Department of Mathematics and Computation School of Science and Technology São Paulo State University (UNESP) Roberto Simonsen street, 305 Presidente Prudente, SP, 19060-900, BRAZIL | - |
dc.description.affiliationUnesp | Department of Computer Engineering and Industrial Automation School of Electrical and Computer Engineering State University of Campinas (UNICAMP) Av. Albert Einstein, 400, Cid. Universitária Zeferino Vaz Distrito Barão Geraldo, Campinas, SP, 13083-852, BRAZIL | - |
dc.description.affiliationUnesp | Electronics Department University Alcala DO-217. Polytechnic School Ctra. Madrid - Barcelona km. 33.6 Alcalá de Henares, Madrid, 28871, SPAIN | - |
dc.identifier.doi | http://dx.doi.org/10.12732/ijam.v26i2.10 | - |
dc.rights.accessRights | Acesso aberto | - |
dc.relation.ispartof | International Journal of Applied Mathematics | - |
dc.identifier.lattes | 7578944173575239 | - |
Appears in Collections: | Artigos, TCCs, Teses e Dissertações da Unesp |
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