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http://acervodigital.unesp.br/handle/11449/39510Registro de metadados completo
| Campo DC | Valor | Idioma |
|---|---|---|
| dc.contributor.author | Marranghello, N. | - |
| dc.contributor.author | Arabnia, H. R. | - |
| dc.date.accessioned | 2014-05-20T15:30:03Z | - |
| dc.date.accessioned | 2016-10-25T18:05:26Z | - |
| dc.date.available | 2014-05-20T15:30:03Z | - |
| dc.date.available | 2016-10-25T18:05:26Z | - |
| dc.date.issued | 2000-01-01 | - |
| dc.identifier | http://www.dcce.ibilce.unesp.br/~norian/publicacoes/pdpta2000.pdf | - |
| dc.identifier.citation | Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, Vols I-v. Athens: C S R E A Press, p. 1539-1544, 2000. | - |
| dc.identifier.uri | http://hdl.handle.net/11449/39510 | - |
| dc.identifier.uri | http://acervodigital.unesp.br/handle/11449/39510 | - |
| dc.description.abstract | This paper presents a configurable architecture which was designed to aid in the simulation of ULSI circuits at the transistor level. Elsewhere [1] this architecture was shown to be able to run such simulations several times as fast as standard circuit simulators such as SPICES. In this paper, after describing the overall idea and the the architecture of the system as a whole, I concentrate on the description of the architecture of the processing elements of the computing array. | en |
| dc.format.extent | 1539-1544 | - |
| dc.language.iso | eng | - |
| dc.publisher | C S R E A Press | - |
| dc.source | Web of Science | - |
| dc.title | A configurable approach to circuit simulation | en |
| dc.type | outro | - |
| dc.contributor.institution | Universidade Estadual Paulista (UNESP) | - |
| dc.description.affiliation | São Paulo State Univ, Dept Comp Sci, BR-15054000 Sao Jose do Rio Preto, Brazil | - |
| dc.description.affiliationUnesp | São Paulo State Univ, Dept Comp Sci, BR-15054000 Sao Jose do Rio Preto, Brazil | - |
| dc.identifier.wos | WOS:000167676300211 | - |
| dc.rights.accessRights | Acesso aberto | - |
| dc.relation.ispartof | Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, Vols I-v | - |
| dc.identifier.orcid | 0000-0003-1086-3312 | pt |
| Aparece nas coleções: | Artigos, TCCs, Teses e Dissertações da Unesp | |
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