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Please use this identifier to cite or link to this item: http://acervodigital.unesp.br/handle/11449/39510
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dc.contributor.authorMarranghello, N.-
dc.contributor.authorArabnia, H. R.-
dc.date.accessioned2014-05-20T15:30:03Z-
dc.date.accessioned2016-10-25T18:05:26Z-
dc.date.available2014-05-20T15:30:03Z-
dc.date.available2016-10-25T18:05:26Z-
dc.date.issued2000-01-01-
dc.identifierhttp://www.dcce.ibilce.unesp.br/~norian/publicacoes/pdpta2000.pdf-
dc.identifier.citationProceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, Vols I-v. Athens: C S R E A Press, p. 1539-1544, 2000.-
dc.identifier.urihttp://hdl.handle.net/11449/39510-
dc.identifier.urihttp://acervodigital.unesp.br/handle/11449/39510-
dc.description.abstractThis paper presents a configurable architecture which was designed to aid in the simulation of ULSI circuits at the transistor level. Elsewhere [1] this architecture was shown to be able to run such simulations several times as fast as standard circuit simulators such as SPICES. In this paper, after describing the overall idea and the the architecture of the system as a whole, I concentrate on the description of the architecture of the processing elements of the computing array.en
dc.format.extent1539-1544-
dc.language.isoeng-
dc.publisherC S R E A Press-
dc.sourceWeb of Science-
dc.titleA configurable approach to circuit simulationen
dc.typeoutro-
dc.contributor.institutionUniversidade Estadual Paulista (UNESP)-
dc.description.affiliationSão Paulo State Univ, Dept Comp Sci, BR-15054000 Sao Jose do Rio Preto, Brazil-
dc.description.affiliationUnespSão Paulo State Univ, Dept Comp Sci, BR-15054000 Sao Jose do Rio Preto, Brazil-
dc.identifier.wosWOS:000167676300211-
dc.rights.accessRightsAcesso aberto-
dc.relation.ispartofProceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, Vols I-v-
dc.identifier.orcid0000-0003-1086-3312pt
Appears in Collections:Artigos, TCCs, Teses e Dissertações da Unesp

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