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DC Field | Value | Language |
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dc.contributor.author | Baldassin, Alexandro José | - |
dc.contributor.author | Goldstein, Felipe | - |
dc.contributor.author | Azevedo, Rodolfo | - |
dc.date.accessioned | 2014-05-20T15:33:24Z | - |
dc.date.accessioned | 2016-10-25T18:09:57Z | - |
dc.date.available | 2014-05-20T15:33:24Z | - |
dc.date.available | 2016-10-25T18:09:57Z | - |
dc.date.issued | 2012-12-01 | - |
dc.identifier | http://dx.doi.org/10.1016/j.jpdc.2012.08.001 | - |
dc.identifier.citation | Journal of Parallel and Distributed Computing. San Diego: Academic Press Inc. Elsevier B.V., v. 72, n. 12, p. 1535-1546, 2012. | - |
dc.identifier.issn | 0743-7315 | - |
dc.identifier.uri | http://hdl.handle.net/11449/42030 | - |
dc.identifier.uri | http://acervodigital.unesp.br/handle/11449/42030 | - |
dc.description.abstract | Single-core architectures have hit the end of the road and industry and academia are currently exploiting new multicore design alternatives. In special, heterogeneous multicore architectures have attracted a lot of attention but developing applications for such architectures is not an easy task due to the lack of appropriate tools and programming models. We present the design of a runtime system for the Cell/BE architecture that works with memory transactions. Transactional programs are automatically instrumented by the compiler, shortening development time and avoiding synchronization mistakes usually present in lock-based approaches (such as deadlock). Experimental results conducted with a prototype implementation and the STAMP benchmark show good scalability for applications with moderate to low contention levels, and whose transactions are not too small. For those cases in which a small performance loss is admissible, we believe that the ease of programming provided by transactions greatly pays off. (C) 2012 Elsevier B.V. All rights reserved. | en |
dc.description.sponsorship | IBM | - |
dc.description.sponsorship | Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) | - |
dc.description.sponsorship | Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) | - |
dc.format.extent | 1535-1546 | - |
dc.language.iso | eng | - |
dc.publisher | Academic Press Inc. Elsevier B.V. | - |
dc.source | Web of Science | - |
dc.subject | Multiprocessors | en |
dc.subject | Parallel programming | en |
dc.subject | Transactional memory | en |
dc.title | A transactional runtime system for the Cell/BE architecture | en |
dc.type | outro | - |
dc.contributor.institution | Universidade Estadual Paulista (UNESP) | - |
dc.contributor.institution | Universidade Estadual de Campinas (UNICAMP) | - |
dc.description.affiliation | Univ Estadual Paulista, UNESP, Rio Claro, Brazil | - |
dc.description.affiliation | Univ Estadual Campinas, UNICAMP, Campinas, SP, Brazil | - |
dc.description.affiliationUnesp | Univ Estadual Paulista, UNESP, Rio Claro, Brazil | - |
dc.description.sponsorshipId | FAPESP: 11/19373-6 | - |
dc.identifier.doi | 10.1016/j.jpdc.2012.08.001 | - |
dc.identifier.wos | WOS:000310669600001 | - |
dc.rights.accessRights | Acesso restrito | - |
dc.relation.ispartof | Journal of Parallel and Distributed Computing | - |
Appears in Collections: | Artigos, TCCs, Teses e Dissertações da Unesp |
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