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Please use this identifier to cite or link to this item: http://acervodigital.unesp.br/handle/11449/67969
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dc.contributor.authorMarranghello, N.-
dc.contributor.authorDe Oliveira, W. L A-
dc.contributor.authorDamiani, F.-
dc.date.accessioned2014-05-27T11:21:12Z-
dc.date.accessioned2016-10-25T18:20:06Z-
dc.date.available2014-05-27T11:21:12Z-
dc.date.available2016-10-25T18:20:06Z-
dc.date.issued2004-12-01-
dc.identifierhttp://dx.doi.org/10.1109/APCCAS.2004.1412692-
dc.identifier.citationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, v. 1, p. 65-68.-
dc.identifier.urihttp://hdl.handle.net/11449/67969-
dc.identifier.urihttp://acervodigital.unesp.br/handle/11449/67969-
dc.description.abstractWe have recently proposed an extension to Petri nets in order to be able to directly deal with all aspects of embedded digital systems. This extension is meant to be used as an internal model of our co-design environment. After analyzing relevant related work, and presenting a short introduction to our extension as a background material, we describe the details of the timing model we use in our approach, which is mainly based in Merlin's time model. We conclude the paper by discussing an example of its usage. © 2004 IEEE.en
dc.format.extent65-68-
dc.language.isoeng-
dc.sourceScopus-
dc.subjectComputational complexity-
dc.subjectComputer hardware-
dc.subjectComputer science-
dc.subjectComputer software-
dc.subjectEmbedded systems-
dc.subjectField programmable gate arrays-
dc.subjectMathematical models-
dc.subjectTiming devices-
dc.subjectCooperative design (co-design)-
dc.subjectDigital systems-
dc.subjectMerlin's time model-
dc.subjectNetworks on chip (NoC)-
dc.subjectPetri nets-
dc.titleA petri net based timing model for hardware/software co-design of digital systemsen
dc.typeoutro-
dc.contributor.institutionUniversidade Estadual Paulista (UNESP)-
dc.contributor.institutionUniversidade Estadual de Campinas (UNICAMP)-
dc.description.affiliationSão Paulo State University-
dc.description.affiliationUniversity of Campinas-
dc.description.affiliationUnespSão Paulo State University-
dc.identifier.doi10.1109/APCCAS.2004.1412692-
dc.identifier.wosWOS:000227668700017-
dc.rights.accessRightsAcesso restrito-
dc.relation.ispartofIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS-
dc.identifier.scopus2-s2.0-13444251353-
dc.identifier.orcid0000-0003-1086-3312pt
Appears in Collections:Artigos, TCCs, Teses e Dissertações da Unesp

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