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Please use this identifier to cite or link to this item: http://acervodigital.unesp.br/handle/11449/71347
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dc.contributor.authorMarranghello, Norian-
dc.contributor.authorDa Silva, Alexandre C.R.-
dc.contributor.authorPereira, Aledir S.-
dc.date.accessioned2014-05-27T11:24:05Z-
dc.date.accessioned2016-10-25T18:27:52Z-
dc.date.available2014-05-27T11:24:05Z-
dc.date.available2016-10-25T18:27:52Z-
dc.date.issued2009-12-01-
dc.identifierhttp://dx.doi.org/10.3182/20091006-3-ES-4010.00017-
dc.identifier.citationIFAC Proceedings Volumes (IFAC-PapersOnline), v. 4, n. PART 1, p. 84-89, 2009.-
dc.identifier.issn1474-6670-
dc.identifier.urihttp://hdl.handle.net/11449/71347-
dc.identifier.urihttp://acervodigital.unesp.br/handle/11449/71347-
dc.description.abstractThe constant increase in digital systems complexity definitely demands the automation of the corresponding synthesis process. This paper presents a computational environment designed to produce both software and hardware implementations of a system. The tool for code generation has been named ACG8051. As for the hardware synthesis there has been produced a larger environment consisting of four programs, namely: PIPE2TAB, AGPS, TABELA, and TAB2VHDL. ACG8051 and PIPE2TAB use place/transition net descriptions from PIPE as inputs. ACG8051 is aimed at generating assembly code for the 8051 micro-controller. PIPE2TAB produces a tabular version of a Mealy type finite state machine of the system, its output is fed into AGPS that is used for state allocation. The resulting digital system is then input to TABELA, which minimizes control functions and outputs of the digital system. Finally, the output generated by TABELA is fed to TAB2VHDL that produces a VHDL description of the system at the register transfer level. Thus, we present here a set of tools designed to take a high-level description of a digital system, represented by a place/transition net, and produces as output both an assembly code that can be immediately run on an 8051 micro-controller, and a VHDL description that can be used to directly implement the hardware parts either on an FPGA or as an ASIC.en
dc.format.extent84-89-
dc.language.isoeng-
dc.sourceScopus-
dc.subjectDesign automation-
dc.subjectDigital system synthesis-
dc.subjectFinite state machine-
dc.subjectPetri net-
dc.subjectAssembly code-
dc.subjectCode Generation-
dc.subjectComputational environments-
dc.subjectControl functions-
dc.subjectDesign automations-
dc.subjectDigital system-
dc.subjectDigital system design-
dc.subjectHardware implementations-
dc.subjectHardware synthesis-
dc.subjectHigh level description-
dc.subjectPlace/transition Petri nets-
dc.subjectRegister transfer level-
dc.subjectSynthesis process-
dc.subjectVHDL description-
dc.subjectAutomation-
dc.subjectComputer aided design-
dc.subjectComputer hardware description languages-
dc.subjectFinite automata-
dc.subjectHardware-
dc.subjectMultiprocessing systems-
dc.subjectPetri nets-
dc.subjectSystems analysis-
dc.titleDigital system design process automation using place/transition petri netsen
dc.typeoutro-
dc.contributor.institutionUniversidade Estadual Paulista (UNESP)-
dc.description.affiliationSao Paulo State University, Sao Jose do Rio Preto, SP 15054-000-
dc.description.affiliationSao Paulo State University, Ilha Solteira, SP 15385-000-
dc.description.affiliationUnespSao Paulo State University, Sao Jose do Rio Preto, SP 15054-000-
dc.description.affiliationUnespSao Paulo State University, Ilha Solteira, SP 15385-000-
dc.identifier.doi10.3182/20091006-3-ES-4010.00017-
dc.rights.accessRightsAcesso restrito-
dc.relation.ispartofIFAC Proceedings Volumes (IFAC-PapersOnline)-
dc.identifier.scopus2-s2.0-79960933497-
dc.identifier.orcid0000-0003-1086-3312pt
Appears in Collections:Artigos, TCCs, Teses e Dissertações da Unesp

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