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Please use this identifier to cite or link to this item: http://acervodigital.unesp.br/handle/11449/9667
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dc.contributor.authorOki, N.-
dc.date.accessioned2014-05-20T13:28:56Z-
dc.date.available2014-05-20T13:28:56Z-
dc.date.issued1999-01-01-
dc.identifierhttp://dx.doi.org/10.1109/MWSCAS.1998.759556-
dc.identifier.citation1998 Midwest Symposium on Circuits and Systems, Proceedings. Los Alamitos: IEEE Computer Soc, p. 568-570, 1999.-
dc.identifier.urihttp://hdl.handle.net/11449/9667-
dc.description.abstractIn this paper is presented an implementation of winner-take-all circuit using CMOS technology. In the proposed configuration the inputs are current and the outputs voltage. The simulation results show that the circuit can be a winner if its input is larger than the other by 2 mu A. The simulation also shows that the response time is 100ns at a 0.2pF load capacitance. To demonstrate the functionality of the proposed circuit, a two-input winner take all circuit was built and tested by using discrete CMOS transistor array (CD40071).en
dc.format.extent568-570-
dc.language.isoeng-
dc.publisherIEEE Computer Soc-
dc.sourceWeb of Science-
dc.titleWinner-take-all circuit using CMOS technologyen
dc.typeoutro-
dc.contributor.institutionUniversidade Estadual Paulista (UNESP)-
dc.description.affiliationUNESP, FEIS, DEE, São Paulo, Brazil-
dc.description.affiliationUnespUNESP, FEIS, DEE, São Paulo, Brazil-
dc.identifier.doi10.1109/MWSCAS.1998.759556-
dc.identifier.wosWOS:000079563200132-
dc.rights.accessRightsAcesso restrito-
dc.relation.ispartof1998 Midwest Symposium on Circuits and Systems, Proceedings-
Appears in Collections:Artigos, TCCs, Teses e Dissertações da Unesp

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