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Please use this identifier to cite or link to this item: http://acervodigital.unesp.br/handle/11449/9689
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dc.contributor.authorOliveira, Vlademir J. S.-
dc.contributor.authorOki, Nobuo-
dc.date.accessioned2014-05-20T13:28:58Z-
dc.date.accessioned2016-10-25T16:48:27Z-
dc.date.available2014-05-20T13:28:58Z-
dc.date.available2016-10-25T16:48:27Z-
dc.date.issued2007-01-01-
dc.identifierhttp://dx.doi.org/10.1109/DTIS.2007.4449491-
dc.identifier.citation2007 International Conference on Design & Technology of Integrated Systems In Nanoscale Era. New York: IEEE, p. 52-55, 2007.-
dc.identifier.urihttp://hdl.handle.net/11449/9689-
dc.identifier.urihttp://acervodigital.unesp.br/handle/11449/9689-
dc.description.abstractAn analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 mu m AMS CMOS process and 1.5V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz.en
dc.description.sponsorshipConselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)-
dc.description.sponsorshipFundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)-
dc.format.extent52-55-
dc.language.isoeng-
dc.publisherIEEE-
dc.sourceWeb of Science-
dc.titleLow voltage four-quadrant current multiplier: An improved topology for n-well CMOS processen
dc.typeoutro-
dc.contributor.institutionUniversidade Estadual Paulista (UNESP)-
dc.description.affiliationUniv Estadual Paulista, Dept Engn Eletr, Ilha Solteira, Brazil-
dc.description.affiliationUnespUniv Estadual Paulista, Dept Engn Eletr, Ilha Solteira, Brazil-
dc.identifier.doi10.1109/DTIS.2007.4449491-
dc.identifier.wosWOS:000256296500010-
dc.rights.accessRightsAcesso restrito-
dc.relation.ispartof2007 International Conference on Design & Technology of Integrated Systems In Nanoscale Era-
Appears in Collections:Artigos, TCCs, Teses e Dissertações da Unesp

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