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Please use this identifier to cite or link to this item: http://acervodigital.unesp.br/handle/11449/9725
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dc.contributor.authorOki, N.-
dc.date.accessioned2014-05-20T13:29:01Z-
dc.date.available2014-05-20T13:29:01Z-
dc.date.issued1999-01-01-
dc.identifierhttp://dx.doi.org/10.1109/MWSCAS.1998.759544-
dc.identifier.citation1998 Midwest Symposium on Circuits and Systems, Proceedings. Los Alamitos: IEEE Computer Soc, p. 520-521, 1999.-
dc.identifier.urihttp://hdl.handle.net/11449/9725-
dc.description.abstractIn this paper a new algorithmic of Analog-to-Digital Converter is presented. This new topology use the current-mode technique that allows a large dynamic range and can be implemented in digital CMOS process. The ADC proposed is very small and can handle high sampling rates. Simulation results using a 1.2um CMOS process show that an 8-b ADC can support a sampling rate of 50MHz.en
dc.format.extent520-521-
dc.language.isoeng-
dc.publisherIEEE Computer Soc-
dc.sourceWeb of Science-
dc.titleAn algorithmic of analog-to-digital converter using current-mode and digital CMOS processen
dc.typeoutro-
dc.contributor.institutionUniversidade Estadual Paulista (UNESP)-
dc.description.affiliationUNESP, FEIS, DEE, São Paulo, Brazil-
dc.description.affiliationUnespUNESP, FEIS, DEE, São Paulo, Brazil-
dc.identifier.doi10.1109/MWSCAS.1998.759544-
dc.identifier.wosWOS:000079563200120-
dc.rights.accessRightsAcesso restrito-
dc.relation.ispartof1998 Midwest Symposium on Circuits and Systems, Proceedings-
Appears in Collections:Artigos, TCCs, Teses e Dissertações da Unesp

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