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Please use this identifier to cite or link to this item: http://acervodigital.unesp.br/handle/11449/37896
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dc.contributor.authorDeLima, J. A.-
dc.date.accessioned2014-05-20T15:27:59Z-
dc.date.accessioned2016-10-25T18:02:58Z-
dc.date.available2014-05-20T15:27:59Z-
dc.date.available2016-10-25T18:02:58Z-
dc.date.issued1996-10-01-
dc.identifierhttp://dx.doi.org/10.1016/0038-1101(96)00043-3-
dc.identifier.citationSolid-state Electronics. Oxford: Pergamon-Elsevier B.V., v. 39, n. 10, p. 1524-1525, 1996.-
dc.identifier.issn0038-1101-
dc.identifier.urihttp://hdl.handle.net/11449/37896-
dc.identifier.urihttp://acervodigital.unesp.br/handle/11449/37896-
dc.format.extent1524-1525-
dc.language.isoeng-
dc.publisherElsevier B.V.-
dc.sourceWeb of Science-
dc.titleEffective aspect-ratio and gate-capacitance in circular geometry MOS transistorsen
dc.typeoutro-
dc.contributor.institutionUniversidade Estadual Paulista (UNESP)-
dc.description.affiliationUNIV ESTADUAL PAULISTA,DEPT ELECT ENGN,BR-12500000 GUARATINGUETA,SP,BRAZIL-
dc.description.affiliationUnespUNIV ESTADUAL PAULISTA,DEPT ELECT ENGN,BR-12500000 GUARATINGUETA,SP,BRAZIL-
dc.identifier.doi10.1016/0038-1101(96)00043-3-
dc.identifier.wosWOS:A1996VJ86600019-
dc.rights.accessRightsAcesso restrito-
dc.relation.ispartofSolid-state Electronics-
Appears in Collections:Artigos, TCCs, Teses e Dissertações da Unesp

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